Allwinner /D1H /SMHC[0] /SMHC_RINTSTS

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Interpret as SMHC_RINTSTS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE)RE 0 (CC)CC 0 (DTC)DTC 0 (DTR)DTR 0 (DRR)DRR 0 (RCE)RCE 0 (DCE)DCE 0 (RTO_BACK)RTO_BACK 0 (DTO_BDS)DTO_BDS 0 (DSTO_VSD)DSTO_VSD 0 (FU_FO)FU_FO 0 (CB_IW)CB_IW 0 (DSE_BC)DSE_BC 0 (ACD)ACD 0 (DEE)DEE 0 (SDIOI_INT)SDIOI_INT 0 (CARD_INSERT)CARD_INSERT 0 (CARD_REMOVAL)CARD_REMOVAL

Description

Raw Interrupt Status Register

Fields

RE

Response Error

CC

Command Complete

DTC

Data Transfer Complete

DTR

Data Transmit Request

DRR

Data Receive Request

RCE

Response CRC Error

DCE

Data CRC Error

RTO_BACK

Response Timeout/Boot ACK Received

DTO_BDS

Data Timeout/Boot Data Start

DSTO_VSD

Data Starvation Timeout/V1.8 Switch Done

FU_FO

FIFO Underrun/Overflow

CB_IW

Command Busy and Illegal Write

DSE_BC

Data Start Error/Busy Clear

ACD

Auto Command Done

DEE

Data End-bit Error

SDIOI_INT

SDIO Interrupt

CARD_INSERT

Card Inserted

CARD_REMOVAL

Card Removed

Links

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